1. Field of the Invention
The present invention relates generally to a radio frequency (RF) system, and more particularly to the integration of a power amplifier section used for an RF system.
2. Description of the Related Art
Recently, the trend of a radio frequency (RF) system is being focused on “RF system on-chip”. Accordingly, a monolithic microwave integrated circuit (MMIC) technique and a complementary metal oxide semiconductor (CMOS) technique are attracting attention. The MMIC technique enables that passive components such as resistors, inductors, and capacitors and active components such as transistors and field effect transistors (FETs) are manufactured on one semiconductor substrate through an integrated process and the CMOS technique enables that all logical circuits and all high-frequency RF analog circuits are realized on one chip at a low price. In particular, although the CMOS technique may be determined as an ultimate technique in which all logical circuits and all high-frequency RF analog circuits can be realized on one chip at a low price, the CMOS technique is not stabilized due to a noise characteristic in high frequencies exceeding 1 GHz and parasitic signals between parts of the CMOS. However, as an RF technique has developed, it is expected that most of circuits inside of a cellular terminal will be included in three or four chips according to a CMOS RF IC technique in a few years.
Although every effort for integration of an RF system is being continuously made so that the RF system can have a high efficiency and a high linear characteristic in a small size as described above, the integration of a power amplifier section raises a question in the RF system. More specifically, in the integration through the CMOS technique, CMOS on-chip is not achieved by using group III or IV compounds because power efficiency is reduced due to a low drain-gate, drain-source, or drain-substrate breakdown voltage of a CMOS and a low resistivity of a substrate. However, recently, power amplifiers have been developed that overcome the disadvantage of a CMOS. Hereinafter, circuits integrated using the CMOS will be described with reference to the accompanying drawings.
FIG. 1 is a circuit diagram illustrating a conventional power amplifier. Referring to FIG. 1, the traditional power amplifier performs matching with respect to an input signal through an input matching network and carries out 1:n matching with respect to an output signal through an impedance transformation section 100. Such an impedance transformation section 100 may be formed using an LC resonant impedance transformation network illustrated in FIG. 2A.
FIG. 2B illustrates a smith chart showing impedance transformation of the LC resonant impedance transformation network illustrated in FIG. 2A.
Although the power amplifier illustrated in FIG. 1 has a simple structure, it is difficult to realize an “on-chip structure” using one chip due to the use of lumped elements. In addition, although the power amplifier is realized as the “on-chip” according to a CMOS technique, it is difficult to solve a problem of loss due to a substrate. Furthermore, it is necessary to use an external choke inductor and a bypass capacitor. Because transistors are concentrated on one spot, high temperature heat is generated, degrading the reliability of the power amplifier.
FIG. 3 is a circuit diagram illustrating a conventional power amplifier disclosed in U.S. Pat. No. 6,359,513. The conventional power amplifier disclosed in U.S. Pat. No. 6 359,513 illustrated in FIG. 3 is constructed using the LC resonant impedance transformation network based on a differential push-pull theory.
Although the power amplifier illustrated in FIG. 1 can be realized in an on-chip inductor structure, remarkable power consumption occurs due to a low substrate resistivity and a serious metal ohmic loss of the power amplifier. In addition, a great amount of heat occurs because transistors are concentrated on one spot, and a problem of a break down voltage may occur because a great drain voltage is applied to all transistors. Furthermore, the size of the power amplifier may increase because a chalk inductor and a bypass capacitor are used for a drain stage of a transistor.
Referring to FIG. 3, a class F power amplifier is realized through the CMOS technique, and this amplifier removes even order harmonics in a differential push-pull structure. Accordingly, this amplifier does not require an additional circuit for the second harmonic tuning, and is designed to reduce the third harmonic by controlling the phase of a differential input. However, even this amplifier causes power consumption due to passive components.
The structure of “DAT (Distributed active transformer)” disclosed in U.S. Pat. No. 6,737,948, which is illustrated in FIG. 4, has been suggested by compensating for structural disadvantages of three amplifiers such as a power amplifier through LC matching described above, a power amplifier in the structure of a “on chip spiral transformer”, and a power amplifier in a CMOS push-pull structure.
The conventional amplifier illustrated in FIG. 4 has the same advantages as the differential push-full power amplifier illustrated in FIG. 3 and the structure enabling CMOS on-chip. In addition, transistors are not concentrated but distributed, so the amplifier can be strong against a breakdown voltage and a temperature. However, the power amplifier illustrated in FIG. 4 degrades the efficiency thereof because a K factor (coupling coefficient) has a value within the range of 0.5 to 06. Furthermore, a quality factor of secondary winding Q2 must be lowered in accordance with an impedance transformation ratio.
In addition, the power amplifier illustrated in FIG. 4 has a current crowding effect and generates an unbalanced input signal due to input feed line coupling, thereby causing serious performance degradation.